This invention relates generally to improved methods and apparatus for generating a memory address in a data processing system and more particularly to improved methods and apparatus for generating a relatively large virtual or logical address in a data processing system employing virtual or mapped data storage. The most direct approach to generating a large address is to provide a data processor having sufficiently wide data paths to accommodate all of the bits of the address. However, the hardware required for such an approach would be quite expensive.
Another known approach is to provide relatively narrow data paths in the data processor and to then provide for making multiple passes of these narrow data paths in order to manipulate addresses wider than the data paths. The difficulty with this multiple pass approach is that the requirement for these multiple passes results in a significant slow-down in operating speed.
One way of overcoming the disadvantages of the multiple pass approach summarized above is disclosed in U.S. Pat. No. 4,251,860 issued Feb. 17, 1981, G. R. Mitchell et al., inventors. In this patent, an embodiment is disclosed which permits the use of relatively narrow data widths while avoiding the need for multiple passes in order to produce a large virtual address. This is accomplished by splitting the base address registers which contain the data that is used to form the virtual address into segment registers and offset registers. Then, opertion is provided so that only the offset portion of a selected base address is required to participate in arithmetic operations in order to form a virtual address, thereby permitting narrow data paths to be used even though the generated virtual address is much wider.
Additional background information regarding addressing techniques can be found in U.S. Pat. No. 4,240,139, issued Dec. 16, 1980; in the article "Indexed Mapping Extends Microprocessor Addressing Range", Ian LeMair, Computer Design, August 1980, pp. 111-118; in the article "Storage Relocation Translator", P. L. Martinez, IBM Technical Disclosure Bulletin, Vol. 23, No. 5, October 1980, pp. 1785-1789; in the article "Relocation Translator Address Bit Scheme", P. L. Martinez, IBM Technical Disclosure Bulletin, Vol. 23, No. 6, November 1980, pp. 2199 and 2200; and in the references cited in the above patent and articles.